This invention relates to the use of decoupling capacitors between the power and the ground planes on a multilayer package.
Decoupling capacitors are often used in semiconductor packages. A decoupling capacitance between the power and the ground planes can reduce the amplitude of the transient voltage on the voltage supply. The transient voltages are caused by current spikes which occur when transistors on the semiconductor circuit switch on or off.
The article "High Frequency Bypass and Decoupling Design", Laudie Doubrava, Proceedings of PowerCon 5., p. H1-1 through H1-11, gives the equation for the maximum transient voltage due to a current surge to be: ##EQU1## , where L is the total inductance seen by the current source, I.sub.P is the peak current demand and C.sub.L is the decoupling capacitance. This equation shows that the greatest transient voltage decreases as the decoupling capacitance is increased.
In multi-layer packages, especially in ceramic packages, a dielectric material separates the power and ground plane. This dielectric material has a certain capacitance depending on the material's dielectric constant. Dielectric materials used in traditional packages include FR4 with a dielectric constant, .epsilon..sub.r =4.2; polyimide with a dielectric constant, .epsilon..sub.r =4; alumina with dielectric constant, .epsilon..sub.r =10; and aluminum nitrate (AlN) with a dielectric constant, .epsilon..sub.r =8.5. The decoupling capacitance between the power and ground plane on a multilayer package with a standard package geometry is about 500 pF using FR4 and about 1,000 pF using alumina. These dielectric materials do not effectively decouple the noise or transient voltage between the power and ground plane. As a result, chip capacitors are typically added to the back side of the package to enhance the decoupling capacitance.
FIG. 1 shows a top diagramic view of a background art package with external chip capacitors. One difficulty with this type of external chip capacitor is that vias must be formed into the package down to the power and ground planes for each of the external decoupling capacitors. Additionally, as shown in FIG. 1, the chip capacitor locations 10 are some distance from the die location 12. Yield problems may occur as a result of added inductance of the traces connecting the distant chip capacitors to the die.
It is an object of the present invention to have an improved package with an increased decoupling capacitance. It is another object of the present invention to have an improved package that does not use external decoupling capacitors.